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1 4 meg x 16 syncflash ?2001, micron technology, inc. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 4 meg x 16 syncflash memory products and specifications discussed herein are subject to change by micron without notice. syncflash ? memory features ? 100 mhz sdram-compatible read timing ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access ? programmable burst lengths: 1, 2, 4, 8, or full page (read) ? lvttl-compatible inputs and outputs ? single +3.3v 0.3v power supply C additional v hh hardware protect mode (rp#) ? four-bank architecture supports true concurrent operations with zero latency: read from any bank while performing a program or erase operation to any other bank ? deep power-down mode: 300a maximum ? cross-compatible flash memory command set ? industry-standard, sdram-compatible pinouts C pins 36 and 40 are no connects for sdram options marking ? configuration 4 meg x 16 (1 meg x 16 x 4 banks) 4m16 ? read timing (cycle time) 10ns (100 mhz) -10 12ns (83 mhz) -12 ? package 54-pin ocpl 1 tsop ii (400 mil) tg ? operating temperature range commercial temperature (0oc to +70oc) none note: 1. off-center parting line part number example: MT28S4M16LCtg-10 pin assignment (top view) MT28S4M16LC 1 meg x 16 x 4 banks 54-pin tsop ii note: the # symbol indicates signal is active low. v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc dqml we# cas# ras# cs# ba0 ba1 a10 a0 a1 a2 a3 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 v ss rp# dqmh clk cke v cc p a11 a9 a8 a7 a6 a5 a4 v ss general description this syncflash ? data sheet is divided into two ma- jor sections. the sdram interface functional description details compatibility with the sdram memory, and the flash memory functional descrip- tion specifies the symmetrical-sectored flash architec- ture functional commands. key timing parameters speed clock access time setup hold grade frequency cl = 2* cl = 3* time time -10 100 mhz C 7ns 3ns 2ns -10 66 mhz 9ns C 3ns 2ns -12 83 mhz C 9ns 3ns 2ns -12 66 mhz 10ns C 3ns 2ns *cl = cas (read) latency the MT28S4M16LC is a nonvolatile, electrically sec- tor-erasable (flash), programmable memory contain- ing 67,108,864 bits organized as 4,194,304 words (16 bits). syncflash memory is ideal for 3.3v-only plat- forms that require both hardware and software protec- tion modes. additional hardware protection modes are
2 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory general description (continued) also available when v hh is applied to the rp# pin. pro- gramming or erasing the device is done with a 3.3v v cc p voltage, while all other operations are performed with a 3.3v v cc . the device is fabricated with microns advanced cmos floating-gate process. the MT28S4M16LC is organized into 16 indepen- dently erasable blocks. to ensure that critical firmware is protected from accidental erasure or overwrite, the MT28S4M16LC features sixteen 256k-word hardware- and software-lockable blocks. the MT28S4M16LC four-bank architecture supports true concurrent operations. a read access to any bank can occur simultaneously with a background pro- gram or erase operation to any other bank. the syncflash memory has a synchronous inter- face (all signals are registered on the positive edge of the clock signal, clk). read accesses to the memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, followed by a read command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coinci- dent with the read command are used to select the starting column location for the burst access. the syncflash memory provides for programmable read burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. the 4 meg x 16 syncflash memory uses an internal pipelined architecture to achieve high-speed operation. the 4 meg x 16 syncflash memory is designed to operate in 3.3v, low-power memory systems. a deep power-down mode is provided, along with a power- saving standby mode. all inputs and outputs are lvttl-compatible. syncflash memory offers substantial advances in flash operating performance, including the ability to synchronously burst data at a high data rate with auto- matic column-address generation and the capability to randomly change column addresses on each clock cycle during a burst access. please refer to microns web site ( www.micron.com/ flash ) for the latest data sheet.
3 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory table of contents functional block diagram C 4 meg x 16 ............... 4 pin descriptions ...................................................... 5 sdram interface functional description .......... 7 initialization ...................................................... 7 register definition ............................................ 7 mode register ............................................... 7 burst length ............................................ 7 burst type ............................................... 7 cas latency ............................................ 9 operating mode ...................................... 9 write burst mode .................................... 9 commands ........................................................ 10 truth table 1 (commands and dqm operation) ....... 10 truth table 2 (commands sequences) ....................... 11 command inhibit ........................................ 13 no operation (nop) .................................... 13 load mode register ...................................... 13 active ............................................................ 13 read .............................................................. 13 write ............................................................. 13 active terminate .......................................... 13 burst terminate ............................................ 13 load command register ............................. 13 operation .......................................................... 14 bank/row activation .................................. 14 reads ............................................................ 15 writes ........................................................... 20 active terminate .......................................... 20 power-down ................................................ 20 clock suspend ............................................. 20 burst read/single write ............................... 21 truth table 3 (cke) .................................................. 21 truth table 4 (current state, same bank) .................. 22 truth table 5 (current state, different bank) ............. 23 flash memory functional description ............... 24 command interface .................................... 24 memory architecture ................................... 24 protected blocks ........................................... 24 command execution logic (cel) ............... 25 internal state machine (ism) ...................... 25 ism status register ...................................... 25 output (read) operations .............................. 25 memory array ............................................. 25 status register .............................................. 25 device configuration registers ................... 25 input operations .............................................. 26 memory array ............................................. 26 command execution ........................................ 26 status register .............................................. 27 device configuration .................................. 27 program sequence ....................................... 27 erase sequence ............................................. 27 program and erase nvmode register ......... 27 block protect/unprotect sequence .............. 27 device protect sequence .............................. 28 reset/deep power-down mode ....................... 28 error handling .................................................. 28 program/erase cycle endurance ................ 28 absolute maximum ratings .................................. 35 dc electrical characteristics and operating conditions ................................... 35 i cc specifications and conditions .......................... 36 capacitance ............................................................ 36 electrical characteristics and recommended operating conditions (timing table) ............. 37 ac functional characteristics ............................. 38 notes ...................................................................... 39 timing waveforms initialize and load mode register ..................... 40 clock suspend mode ......................................... 41 reads read .............................................................. 42 alternating bank read accesses ................... 43 read C full-page burst ................................. 44 read C dqm operation .............................. 45 program program/erase (bank a followed by read to bank b ).. 46 program/erase (bank a followed by read to bank a ).. 47
4 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory functional block diagram 4 meg x 16 ras# cas# row- address mux clk cs# we# cke column- address counter/ latch 8 a0Ca11, ba0, ba1 dqml, dqmh 12 address register 14 256 (x16) 4,096 i/o gating dqm mask logic read data latch write drivers column decoder bank 0 memory array (4,096 x 256 x 16) bank 0 row- address latch & decoder high voltage switch/pump 4,096 sense amplifiers bank control logic dq0Cdq15 16 16 16 12 bank 1 bank 2 bank 3 12 8 2 2 2 command execution logic mode register command decode state machine status reg. nvmode register 16 data input register data output register rp# v cc p id reg.
5 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory pin descriptions 54-pin tsop numbers symbol type description 38 clk input clock: clk is driven by the system clock. all syncflash memory input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. 37 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides standby operation or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down modes, providing low standby power. cke may be tied high in systems where power-down modes (other than rp# deep power-down) are not required. 19 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 18, 17, 16 ras#, input command inputs: ras#, cas#, and we# (along with cs#) define the cas#, command being entered. we# 15, 39 dqml, input input/output mask: dqm is an input mask signal for write accesses dqmh and an output enable signal for read accesses. input data is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high-z state (after a two-clock latency) when dqm is sampled high during a read cycle. dqml corresponds to dq0Cdq7 and dqmh corresponds to dq8Cdq15. dqml and dqmh are considered same state when referenced as dqm. 23-26, 29-34, a0Ca11 input address inputs: a0Ca11 are sampled during the active command 22, 35 (row-address a0Ca11) and read/write command (column-address a0Ca7) to select one location in the respective bank. the address inputs provide the op-code during load mode register command and the operation code during a load command register command. 40 rp# input initialize/power-down: upon initial device power-up, a 100s delay after rp# has transitioned from low to high is required for internal device initialization, prior to issuing an executable command. rp# clears the status register, sets the internal state machine (ism) to the array read mode, and places the device in the deep power-down mode when low. all inputs, including cs#, are dont care and all outputs are high-z. when rp# = v hh , all protection modes are ignored during program and erase. also allows the device protect bit to be set to 1 (protected) and allows the block protect bits at locations 0 and 15 to be set to 0 (unprotected) when brought to v hh . rp# must be held high during all other modes of operation. (continued on next page)
6 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory 20, 21 ba0, input bank address input(s): ba0, ba1 define to which bank the command ba1 is being applied. see truth tables 1 and 2. 2, 4, 5, 7, 8, 10, dq0- i/o data i/o: data bus. 11,13, 42, 44, 45, dq15 47, 48, 50, 51, 53 3, 9, 43, 49 v cc q supply dq power: provide isolated power to dqs for improved noise immunity. 6, 12, 46, 52 v ss q supply dq ground: provide isolated ground to dqs for improved noise immunity. 1, 14, 27 v cc supply power supply: 3.3v 0.3v. 28, 41, 54 v ss supply ground. 36 v cc p supply program/erase supply voltage: v cc p must be tied externally to v cc . the v cc p pin sources current during device initialization, program and erase operations. pin descriptions (continued) 54-pin tsop numbers symbol type description
7 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram sdram interface functional description in general, the 64mb syncflash memory (1 meg x 16 x 4 banks) is configured as a quad-bank, nonvolatile sdram that operates at 3.3v and includes a synchro- nous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read accesses to the syncflash memory are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. accesses begin with the registra- tion of an active command, followed by a read com- mand. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0Ca11 select the row). the address bits registered coincident with the read command are used to select the starting column location for the burst access (ba0 and ba1 se- lect the bank, a0Ca7 select the column). prior to normal operation, the syncflash memory must be initialized. the following sections provide de- tailed information covering device initialization, regis- ter definition, command descriptions, and device op- eration. initialization syncflash memory must be powered up and initial- ized in a predefined manner. operational procedures other than those specified may result in undefined operation. after power is applied to v cc , v cc q, and v cc p (simultaneously), and the clock is stable, rp# must be brought from low to high. a 100s delay is required after rp# transitions high in order to complete inter- nal device initialization. the syncflash memory is now in the array read mode and ready for mode register programming or an ex- ecutable command. after initial programming of the nvmode register, the contents are automatically loaded into the mode register during initialization and the device will power up in the programmed state. register definition mode register the mode register is used to define the specific mode of operation of the syncflash memory. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode, as shown in fig- ure 1. the mode register is programmed via the load mode register command and will retain the stored information until it is reprogrammed. the contents of the mode register may be copied into the nvmode reg- ister; the mode register settings automatically load the mode register during initialization. details on erase nvmode register and program nvmode register com- mand sequences are found in the command execu- tion section of the flash memory functional descrip- tion. mode register bits m0Cm2 specify the burst length, m3 specifies the burst type (sequential or interleaved), m4Cm6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode in an sdram (m9 = 1 by default), and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read accesses to the syncflash memory are burst oriented, with the burst length being programmable, as shown in figure 1. the burst length determines the maximum number of column locations that can be ac- cessed for a given read command. burst lengths of 1, 2, 4, or 8 locations are available for both sequential and interleaved burst types, and a full-page burst is avail- able for the sequential type. the full-page burst is used in conjunction with the burst terminate com- mand to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read command is issued, a block of col- umns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1Ca7 when the burst length is set to two, by a2Ca7 when the burst length is set to four, and by a3Ca7 when the burst length is set to eight. the remaining (least significant) address bit(s) are used to select the start- ing location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type, and the starting column address, as shown in table 1.
8 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram figure 1 mode register definition table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0Ca7 cn, cn+1, cn+2 page cn+3, cn+4... not supported 256 (location 0-255) cn-1, cn... note: 1. for a burst length of two, a1Ca7 select the block- of-two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2Ca7 select the block- of-four burst; a0Ca1 select the starting column within the block. 3. for a burst length of eight, a3Ca7 select the block-of-eight burst; a0Ca2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0Ca7 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0Ca7 select the unique column to be accessed, and mode register bit m3 is ignored. m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved m6 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 a11 10 11 reserved* wb 0 1 write burst mode reserved single location access m9 *program m11, m10 = 0, 0 to ensure compatibility with future devices.
9 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram cas latency the cas latency is the delay, in clock cycles, be- tween the registration of a read command and the availability of the first piece of output data. the la- tency can be set to one, two, or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by figure 2 cas latency table 2 cas latency allowable operating frequency (mhz) cas cas cas speed latency = 1 latency = 2 latency = 3 -10 33 66 100 -12 33 66 83 clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1) and, provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0, and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 2. table 2 below indicates the operat- ing frequencies at which each cas latency setting can be used. reserved states should not be used, as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to read bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode write bursts are not supported with the MT28S4M16LC. by default, m9 is set to 1 and write accesses are single-location (nonburst) accesses. clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop dont care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
10 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram commands truth table 1 provides a quick reference of avail- able commands for sdram-compatible operation. this is followed by a written description of each command. additional truth tables appear later. truth table 1 sdram-compatible interface commands and dqm operation (notes: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 2 read (select bank, column and start read burst) l h l h x bank/col x 3 write (select bank, column and start write) l h l l x bank/col valid 3, 4 burst terminate l h h l x x active active terminate l l h l x x x 5 load command register l l l h x comcode x 6, 7 load mode register l l l l x opcode x 8 write enable/output enable C C C C l C active 9 write inhibit/output high-z C C C C h C high-z 9 note: 1. cke is high for all commands shown. 2. a0Ca11 provide row address, and ba0 and ba1 determine which bank is made active. 3. a0Ca7 provide column address, and ba0 and ba1 determine which bank is being read from or written to. 4. a program setup command sequence (see truth table 2) must be completed prior to executing a write. 5. active terminate is functionally equivalent to the sdram precharge command, however precharge (deactivate row in bank or banks) is not required for syncflash memory. a10 low: ba0 and ba1 determine the bank being active terminated. a10 high: all banks active terminated and ba0 and ba1 are dont care. 6. a0Ca7 define the comcode, and a8Ca11 are dont care for this operation. see truth table 2. 7. load command register (lcr) replaces the sdram auto refresh or self refresh command, which is not required for syncflash memory. lcr is the first cycle for flash memory command sequences. see truth table 2. 8. a0Ca11 define the opcode written to the mode register. the mode register can be dynamically loaded each cycle, provided t mrd is satisfied. the contents of the nvmode register are automatically loaded into the mode register during device initialization. 9. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay).
11 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram commands truth table 2 provides a quick reference of available commands for flash memory interface operation. a written description of each command is found in the flash memory functional description sec- tion. truth table 2 flash memory command sequences (notes: 1, 2, 3, 4, 5; see notes on the next page.) first cycle second cycle third cycle bank bank bank operation cmd addr 6 addr dq rp# cmd 7 addr addr dq rp# cmd addr addr dq 8 rp# notes read device configuration lcr 90h bank x h active row bank x h read ca bank x h 9, 10 read status register lcr 70h x x h active x x x h read x x x h clear status register lcr 50h x x h erase setup/confirm lcr 20h bank x h active row bank x h write x bank d0h h/v hh 11, 12, 13 program setup/program lcr 40h bank x h active row bank x h write col bank d in h/v hh 11, 12, 13 protect block/confirm lcr 60h bank x h active row bank x h write x bank 01h h/v hh 11, 12, 13, 14 protect device/confirm lcr 60h bank x h active x bank x h write x bank f1h v hh 11, 12 unprotect blocks/confirm lcr 60h bank x h active x bank x h write x bank d0h h/v hh 11, 12, 13, 15 erase nvmode register lcr 30h bank x h active x bank x h write x bank c0h h 11, 12 program nvmode register lcr a0h bank x h active x bank x h write x bank x h 11, 12
12 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram note: 1. cmd = command: decoded from cs#, ras#, cas#, and we# inputs. 2. nop/command inhibit commands may be issued throughout any operation command sequence. 3. after a program or erase operation is registered to the ism and prior to completion of the ism operation, a read to any location in the bank under ism control will output the contents of the row activated prior to the lcr/active/write sequence (see note 7). 4. in order to meet the t rcd specification, the appropriate number of nop/command inhibit commands must be issued between active and read/write commands. 5. the erase, program, protect, unprotect operations are self-timed. the status register may be polled to monitor these operations. 6. a8Ca11 are dont care. 7. a row will not be opened when active is preceded by lcr. active is considered a nop. 8. data inputs: dq8Cdq15 are dont care. data outputs: all unused bits are driven low. 9. the block address is required during active and read cycles for the block protect bit location. the first row in a block should be specified, acceptable values include 000h, 400h, 800h, and c00h. bank address is dont care for manufac- turer compatibility id, device id, and device protect bit location. 10. ca = configuration address: 000h C manufacturer compatibility id (2ch) 001h C device id (d3h) x02h C block protect bit, where x = 0, 4, 8, or ch 003h C device protect bit 11. the proper command sequence (lcr/active/write) is needed to initiate an erase, program, protect, unprotect operation. 12. the bank address must match for the three command cycles (lcr/active/write) to initiate an erase, program, protect, unprotect operation. 13. if the device protect bit is set, then an erase, program, protect, unprotect operation can still be initiated by bringing rp# to v hh prior to the write command cycle and holding it at v hh until the operation is completed. 14. the a10, a11 row address and ba0, ba1 bank address select the block to be protected; a0Ca9 are dont care. 15. if the device protect bit is not set, rp# = v ih unprotects all sixteen 256k-word erasable blocks, except for blocks 0 and 15. when rp# = v hh , all sixteen 256k-word erasable blocks (including block 0 and 15) will be unprotected, and the device protect bit will be ignored. if the device protect bit is set and rp# = v ih , the block protect bits cannot be modified.
13 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram command inhibit the command inhibit function prevents new commands from being executed by the syncflash memory, regardless of whether the clk signal is en- abled. the syncflash memory is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a syncflash memory that is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0Ca11 and ba0 and ba1. see mode register heading in register definition section. the load mode register com- mand can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. the data in the nvmode register is automatically loaded into the mode register upon power-up initialization and is the default mode setting unless dynamically changed with the load mode register command. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0Ca11 selects the row. this row remains active for accesses until the next ac- tive command, power-down or reset. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0Ca7 selects the starting column location. read data appears on the dqs subject to the logic level on the dqm input two clocks earlier. if a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was regis- tered low, the dqs will provide valid data. write the write command is used to initiate a single- location write access. a write command must be pre- ceded by lrc/active. the value on the ba0, ba1 in- puts selects the bank, and the address provided on inputs a0Ca7 selects the column location. input data appearing on the dqs is written to the memory array, subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that word/column location. a write command with dqm high is con- sidered a nop. active terminate active terminate, which replaces the sdram precharge command, is not required for syncflash memory, but is functionally equivalent to the sdram precharge command. active terminate can be issued to terminate a burst read in progress and may or may not be bank specific. burst terminate the burst terminate command is used to trun- cate either fixed-length or full-page bursts. the most recently registered read command prior to the burst terminate command will be truncated as shown in the operation section of this data sheet. burst ter- minate is not bank specific. load command register (lcr) the load command register (lcr) command is used to initiate flash memory control commands to the command execution logic (cel). the cel receives and interprets commands to the device. these com- mands control the operation of the ism and the read path (i.e., memory array, id register, or status register). however, there are restrictions on what commands are allowed in this condition. see the command execution section of flash memory functional description for more details.
14 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram figure 3 activating a specific row in a specific bank clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd dont care figure 4 example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 operation bank/row activation before any read or write commands can be is- sued to a bank within the syncflash memory, a row in that bank must be opened. (note: a row will not be activated for lcr/active/read or lcr/active write com- mand sequences, see the flash memory architecture section for additional information). this is accom- plished via the active command, which selects both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specifi- cation of 30ns with a 90 mhz clock (11.11ns period) results in 2.7 clocks rounded to 3. this is reflected in figure 4, which covers any case where 2 < t rcd (min)/ t ck 3 . (the same procedure is used to convert other specification limits from time units to clock cycles). a subsequent active command to a different row in the same bank can be issued without having to close a previous active row, provided the minimum time in- terval between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. cs# we# cas# ras# cke clk a0Ca10 row address high ba0, ba1 bank address
15 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram reads read bursts are initiated with a read command, as shown in figure 5. the starting column and bank addresses are pro- vided with the read command. during read bursts, the valid data-out element from the starting column address will be available fol- lowing the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 6 shows general timing for one, two, and three cas latency settings. upon completion of a burst, assuming no other com- mands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncated with a subsequent read command, and data from a fixed- length read burst may be immediately followed by data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst that is being truncated. figure 5 read command figure 6 cas latency the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 7 for cas latencies of one, two, and three; data element n + 3 is either the last of a burst of four, or the last desired of a longer burst. the syncflash memory uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initi- ated on any clock cycle following a previous read com- mand. full-speed, random read accesses within a page can be performed as shown in figure 8, or each subse- quent read may be performed to a different bank. data from any read burst may be truncated with a cs# we# cas# ras# cke clk column address a0Ca7 ba0, ba1 bank address high clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop dont care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
16 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram figure 7 consecutive read bursts clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n dont care nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles note: each read command may be to either bank. dqm is low. cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3
17 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram figure 8 random read accesses within a page clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n dont care d out n d out a d out x d out m read note: each read command may be to either bank. dqm is low. read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cas latency = 1 cas latency = 2 cas latency = 3
18 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram figure 9 read to write subsequent write command (write commands must be preceded by lcr/active), and data from a fixed-length read burst may be immediately followed by data from a subsequent write command (subject to bus turnaround limitations). the write may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be the possibility that the device driving the input data would go low-z before the syncflash memory dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention as shown in figure 9. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to sup- press data-out from the read. once the write com- mand is registered, the dqs will go high-z (or remain high-z) regardless of the state of the dqm signal. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buff- ers) to ensure that the written data is not masked. fig- ure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle. a fixed-length or full-page read burst can be trun- cated with active terminate (may or may not be bank specific) or burst terminate (not bank spe- cific). the active terminate or burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 10 for each possible cas latency; data element n + 3 is the last desired data element of a burst of four or the last desired of a longer burst. read lcr active write nop clk t2 t1 t4 t3 t0 dqm, h dq d out n command d in b address bank, col n bank, col b ds t hz t t ck note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. if a cas latency of one is used, then dqm is not required. dont care 40h bank row
19 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram figure 10 terminating a read burst clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 dont care note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles
20 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram writes a single-location write is initiated with a write command (preceded by lcr/active, see truth table 2), as shown in figure 11. the starting column and bank addresses are provided with the write com- mand. once a write command is registered, a read command can be executed as defined by truth tables 4 and 5. an example is shown in figure 12. during a write, the valid data-in element will be registered coincident with the write command. addi- tional details on write sequence operations are found in the command execution section. active terminate the active terminate command is functionally equivalent to the sdram precharge command. un- like sdram, syncflash does not require a precharge command to deactivate the open row in a particular bank or the open rows in all banks. asserting input a10 high during an active terminate command will terminate a burst read in any bank. when a10 is low during an active terminate command, ba0 and ba1 will determine which bank will undergo a ter- minate operation. active terminate is considered a nop for banks not addresssed by a10, ba0, ba1. figure 12 write to read burst read/single write the burst read/single write mode is the default mode for the MT28S4M16LC; the write burst mode bit (m9) in the mode register is set to a logic 1. all write commands result in the access of a single column loca- tion (burst of one). read commands access columns according to the programmed burst length and se- quence. power-down power-down occurs if cke is registered low coinci- dent with a nop or command inhibit, when no accesses are in progress. entering power-down deacti- vates the input and output buffers (excluding cke) after ism operations (including write operations) are completed, for power savings while in standby. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see the reset/deep power-down description in the flash memory functional description for maximum power savings mode. clock suspend the clock suspend mode occurs when a column ac- cess/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, freezing the synchronous logic. figure 11 write command cs# we# cas# ras# cke clk column address a0Ca7 ba0, ba1 bank address high clk dq t2 t1 t3 t0 command address read dont care write bank, col n d in n nop nop bank, col b note: a cas latency of two is used for illustration. the write command may be to any bank and the read command may be to any bank. dqm is low. for more details, refer to truth tables 4 and 5. db out
21 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram figure 14 clock suspend during read burst truth table 3 C cke (notes: 1-4) cke n-1 cke n current state command n action n notes l l clock standby x maintain clock standby clock suspend x maintain clock suspend l h clock standby command inhibit or nop exit clock standby 5 clock suspend x exit clock suspend 6 h l no burst in progress command inhibit or nop clock standby reading valid clock suspend h h see truth table 4 note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the syncflash memory immediately prior to clock edge n . 3. command n is the command registered at clock edge n and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the idle state in time for clock edge n + 1 (provided that t cks is met). 6. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1 . t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) coming out of a power-down sequence (active), t cks (cke setup time) must be greater than or equal to 3ns. figure 13 power-down dont care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 note: for this example, cas latency = 2, burst length = 4 or greater, and dm is low. cke internal clock nop for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the in- put pins at the time of a suspended internal clock edge is ignored, any data present on the dq pins remains driven, and burst counters are not incremented, as long as the clock is suspended (see example in figure 14). clock suspend mode is exited by registering cke high; the internal clock and related operation will re- sume on the subsequent positive clock edge.
22 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram truth table 4 C current state bank n ; command to bank n (notes: 1-6) current state cs# ras# cas# we# command/action notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) l l h h active (select and activate row) idle l l l h load command register llll load mode register 7 l l h l active terminate 8 l h l h read (select column and start read burst) row active l h l l write (select column and start write) l l h l active terminate 8 l l l h load command register l h l h read (select column and start new read burst) read l l h l active terminate 8 l h h l burst terminate 9 l l l h load command register write l h l h read (select column and start new read burst) 10 l l l h load command register note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 3). 2. this table is bank specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank, when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank is not in read or write mode. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated and has not yet terminated or been terminated. write: a write operation has been initiated to the syncflash ism and has not yet completed. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table 4, and according to truth table 5. active terminate: starts with registration of an active terminate command and ends on the next clock cycle. the bank will then be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the syncflash memory will be in the all banks idle state. initialize mode: starts with rp# transitioning from low to high and ends after 100s delay. 6. all states and sequences not shown are illegal or reserved. 7. not bank specific; requires that all banks are idle. 8. may or may not be bank specific. 9. not bank specific; burst terminate affects the most recent read burst, regardless of bank. 10. a read operation to the bank under ism control will output the contents of the row activated prior to the lcr/active/ write sequence (see truth table 2).
23 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory sdram truth table 5 C current state bank n; command to bank m (notes: 1-6) current state cs# ras# cas# we# command/action notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m l l h h active (select and activate row) row activating, l h l h read (select column and start read burst) active, or l h l l write (select column and start write) active l l h l active terminate terminate l l l h load command register l l h h active (select and activate row) read l h l h read (select column and start new read burst) l l h l active terminate l l l h load command register l l h h active (select and activate row) l h l h read (select column and start read burst) write l l h l active terminate l h h l burst terminate l l l h load command register note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 3). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank is not in initialize, read, write mode. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated and has not yet terminated or been terminated. write: a write operation has been initiated to the syncflash ism and has not yet completed. 4. load mode register command may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved.
flash 24 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory flash memory functional description the syncflash memory incorporates a number of features that make it ideally suited for code storage and execute-in-place applications on an sdram bus. the memory array is segmented into individual erase blocks. each block may be erased without affecting data stored in other blocks. these memory blocks are read, programmed, and erased by issuing commands to the command execution logic (cel). the cel con- trols the operation of the internal state machine (ism), which completely controls all erase nvmode regis- ter, program nvmode register, program, block erase, block protect, device protect, unprotect all blocks, and verify operations. the ism protects each memory location from overerasure and optimizes each memory location for maximum data retention. in addition, the ism greatly simplifies the control necessary for programming the device in-system or in an external programmer. the flash memory functional description provides detailed information on the operation of the syncflash memory and is organized into these sections: ? command interface ? memory architecture ? output (read) operations ? input operations ? command execution ? reset/power-down mode ? error handling ? program/erase cycle endurance command interface all flash operations are executed with lcr (load command register), lcr/active/read, or lcr/ active/write commands and command sequences as defined in truth tables 1 and 2. see the sdram interface functional description for information on reading the memory array. address pins a0Ca7 are used to input 8-bit com- mands during the lcr command cycle. this command will identify which flash operation is initiated. certain lcr/active/write command sequences re- quire an 8-bit confirmation code on the write cycle. the confirmation code is input on dq0Cdq7. all input commands are latched on the positive clock edge. memory architecture the 64mb syncflash is a four-bank architecture with four erasable blocks per bank. by erasing blocks rather than the entire array, the total device endur- ance is enhanced, as is system flexibility. only the erase and block protect functions are block ori- ented. the four banks have simultaneous read-while- write functionality. an ism program or erase opera- tion to any bank can occur simultaneously with a read to any other bank. the syncflash memory has a single background operation ism to control power-up initialization, erase, program, and protect operations. ism operations are initiated with an lcr/active/write command sequence. only one ism operation can occur at any time; however, certain other commands, includ- ing read operations, can be performed while an ism operation is taking place. a new lcr/active/write com- mand sequence will not be permitted until the current ism operation is complete. an operational command controlled by the ism is defined as either a bank-level operation or a device-level operation. program and erase are bank-level ism opera- tions. after an ism bank-level operation has been initi- ated, a read may be issued to any bank; however, a read to the bank under ism control will output the contents of the row activated prior to the lcr/active/ write command sequence. erase nvmode register, program nvmode register, block protect, device protect, and unprotect all blocks are device-level ism opera- tions. once an ism device-level operation has been initiated, a read to any bank will output the contents of the array. a read status register command sequence may be issued to determine completion of the ism operation. when sr7 = 1, the ism operation is complete and a new ism operation may be initiated. protected blocks the 64mb syncflash memory is organized into 16 erasable memory blocks. each block may be software protected by issuing the appropriate lcr/active/write sequence for a block protect operation. the blocks at locations 0 and 15 have additional protection to prevent inadvertent program or erase operations in 3.3v-only platforms. once a protect block operation has been executed to these blocks, an unprotect all blocks operation will unlock all blocks except the blocks at locations 0 and 15 unless rp# = v hh . this provides additional security for critical code during in-system firmware updates should an unintentional power disruption or system reset occur.
flash 25 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory a second level of block protection is possible by completing a hardware device protect opera- tion. device protect prevents block protect bit modification. the protection status of any block may be checked by reading the protect bits with a read device configu- ration command sequence. command execution logic (cel) syncflash operations are executed by issuing the appropriate commands to the cel. the cel receives and interprets commands to the device. these com- mands control the operation of the ism and the read path (i.e., memory array, device configuration, or sta- tus register). commands may be issued to the cel while the ism is active. however, there are restrictions on what commands are allowed in this condition. see the command execution section for more details. internal state machine (ism) power-up initialization, erase, program, and pro- tect timings are simplified by using an ism to control all programming algorithms in the memory array. the ism ensures protection against overerasure and optimizes programming margin to each cell. during program operations, the ism automati- cally increments and monitors program attempts, verifies programming margin on each memory cell, and updates the ism status register. when block erase is performed, the ism automatically overwrites the en- tire addressed block (eliminates overerasure), incre- ments and monitors erase attempts, and sets bits in the ism status register. ism status register the 16-bit ism status register allows an external processor to monitor the status of the ism during de- vice initialization, erase nvmode register, pro- gram nvmode register, program, erase, block protect, device protect or unprotect all blocks, and any related errors. ism operations and related errors can be monitored by reading status register bits on dq0Cdq8. all of the defined bits are set by the ism, but only the ism status bits (sr0, sr1, sr2, sr7) are cleared by the ism. the erase/unprotect block, program/protect block, and device protection bits must be cleared by the host system using the clear status register command. this allows the user to choose when to poll and clear the status register. for example, the host system may perform multiple program operations before checking the status register instead of checking after each individual program. a v cc power sequence error is cleared by re- initializing the device. asserting the rp# signal or powering down the de- vice will also clear the status register. figure 15 memory address map 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block bank 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 fff ffh 3 3 bff ffh 3 3 7ff ffh 3 3 3ff ffh 3 000 00h 2 ffh fff c00 2 00h bff 2 ffh 2 800 00h 7ff 2 ffh 400 2 00h 3ff 2 ffh 000 2 00h fff 1 ffh c00 00h 1 bff 1 ffh 800 00h 1 7ff ffh 1 400 00h 1 1 ffh 3ff 000 00h 1 ffh fff 0 c00 0 00h 0 ffh bff 0 00h 800 0 ffh 7ff 0 00h 400 0 ffh 3ff 0 00h 000 bank 1 bank 2 bank 3 unlock blocks (rp# = v hh ) word-wide (x16) unlock blocks (rp# = v ih ) bank column row 00h c00 800 00h 400 00h address range note: see block lock and unlock flowchart sequences for additional information
flash 26 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory output (read) operations syncflash memory features three different types of reads. depending on the mode, a read operation will produce data from the memory array, status regis- ter, or one of the device configuration registers. syncflash memory is in the array read mode unless a status register or device register read is initiated or in progress. a read to the device configuration register or the status register must be preceded by lcr/active. the burst length of data-out is defined by the mode regis- ter settings. reading the device configuration register or status register will not disrupt data in a previously opened (or activated) page. when the burst is com- plete, a subsequent read will read the array. how- ever, several differences exist and are described in the following section. moving between modes to perform a specific read will be covered in the command execu- tion section. memory array a read command to any bank will output the con- tents of the memory array. while a program or erase ism operation is in progress, a read to any location in the bank under ism control will output the contents of the row activated prior to the lcr/active/write com- mand sequence; a read to any other bank will output the contents of the array. all commands and their op- erations are covered in the sdram interface functional description section. status register reading the status register requires an lcr/active/ read command sequence. the status register contents are latched on the next positive clock edge subject to cas latencies. the burst length of the status register data-out is defined by the mode register. all commands and their operations are covered in the command execution section. device configuration registers reading the device id, manufacturer compatibility id, device protection status, and block protect status requires the same input sequencing as when reading the status register except that specific addresses must be issued. all commands and their operations are covered in the command execution section. input operations an lcr/active/write command sequence is re- quired to program the array, or to perform an erase, protect, or unprotect operation. the first cycle of an input operation is lcr where inputs a0Ca7 deter- mine the input command being executed to the cel. an input operation will not disrupt data in a previously opened page. the dq pins are used either to input data to the array or to input a command to the command execu- tion logic (cel) during the write cycle. more information describing how to program, erase, protect, or unprotect the device is provided in the com- mand execution section. memory array programming or erasing the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. setting any bit to a logic 1 re- quires that the entire block be erased. programming a protected block requires that the rp# pin be brought to v hh . a0Ca11 provide the address to be programmed, while the data to be programmed in the array is input on the dq pins. the data and addresses are latched on the rising edge of the clock. details on how to input data to the array is covered in the command execution section. command execution commands are issued to bring the device into dif- ferent operational modes. each mode has specific op- erations that can be performed while in that mode. all modes require that an lcr/active/read or lcr/active/ write sequence be issued, except clear status reg- ister which is a single lcr command. inputs a0Ca7 during the lcr command determine the command being executed. the following section describes the properties of each mode, and truth tables 1 and 2 list all commands and command sequences required to perform the desired operation. read-while-write func- tionality allows a background operation program or erase to any bank while simultanously reading any other bank. the lcr/active/write command sequences in truth table 2 must be completed on consecutive clock cycles. however, in order to reduce bus contention issues, an unlimited number of nops or command inhibits can be issued throughout the lcr/active/write com- mand sequence. for additional protection, these com- mand sequences must have the same bank address for the three command cycles. if the bank address changes during the lcr/ac- tive/write command sequence or if the command se- quences are not consecutive (other than nops and command inhibits), the program and erase status bits (sr4 and sr5) will be set and the desired operation will be aborted.
flash 27 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory status register reading the status register requires an lcr/active/ read command sequence. the status register contents are latched on the next positive clock edge subject to cas latencies for a burst length defined by the mode register. device configuration to read the device id, manufacturer compatibility id, device protect bit, and each of the block protect bits, the appropriate lcr/active/read command se- quence for read device configuration must be issued. specific configuration addresses must be is- sued to read the desired information. the manufac- turer compatibility id is read at 000h; the device id is read at 001h. the manufacturer compatibility id and device id are output on dq0Cdq7. the device protect bit is read at 003h; and each of the block protect bits is read on the third address location within each block (x02h). the device and block protect bits are output on dq0. the device configuration register contents are out- put subject to cas latencies for a burst length defined by the mode register. program sequence three commands on consecutive clock edges are required to input data to the array (nops and com- mand inhibits are permitted between cycles). in the first cycle, load command register is issued with program setup (40h) on a0Ca7, and the bank address is issued on ba0, ba1. the next command is active, which identifies the row address and con- firms the bank address. the third cycle is write, dur- ing which the column address, the bank address, and data are issued. the ism status bit will be set on the following clock edge (subject to cas latencies). while the ism is programming the array, the ism status bit (sr7) will be at 0. when the ism status bit (sr7) is set to a logic 1, programming is complete, and the bank will be in the array read mode and ready for a new ism operation. programming hardware-protected blocks requires that the rp# pin be set to v hh prior to the third cycle (write), and rp# must be held at v hh until the ism program operation is complete. the program and erase status bits (sr4 and sr5) will be set and the op- eration aborted if the lcr/active/write command se- quence is not completed on consecutive cycles or the bank address changes for any of the three cycles. after the ism has initiated programming, it cannot be aborted except by a reset or by powering down the device. doing either while programming the array will corrupt the data being written. erase sequence executing an erase sequence will set all bits within a block to logic 1. the command sequence necessary to execute an erase is similar to that of a program. to provide added security against accidental block era- sure, three consecutive command sequences on con- secutive clock edges are required to initiate an erase of a block. in the first cycle, load command regis- ter is issued with erase setup (20h) on a0Ca7, and the bank address of the block to be erased is issued on ba0, ba1. the next command is active, where a10, a11, ba0, and ba1 provide the address of the block to be erased. the third cycle is write, during which erase confrim (d0h) is issued on dq0Cdq7 and the bank address is reissued. the ism status bit will be set on the following clock edge (subject to cas latencies). after erase confirm (d0h) is issued, the ism will start erasing the addressed block. when the erase operation is complete, the bank will be in the array read mode and ready for an executable command. erasing hardware-protected blocks also requires that the rp# pin be set to v hh prior to the third cycle (write), and rp# must be held at v hh until the erase operation is complete (sr7 = 1). if the lcr/active/write command sequence is not completed on consecutive cycles (nops and command inhibits are permitted between cycles), or the bank address changes for one or more of the command cycles, the program and erase status bits (sr4 and sr5) will be set. program and erase nvmode register the contents of the mode register may be copied into the nvmode register with a program nvmode register command. prior to programming the nvmode register, an erase nvmode register command sequence must be completed to set all bits in the nvmode register to logic 1. the command sequence necessary to execute an erase nvmode register and program nvmode register is similar to that of a program. see truth table 2 for more information on the lcr/active/write commands necessary to complete erase nvmode register and program nvmode register. block protect/unprotect sequence executing a block protect sequence will enable the first level of software/hardware protection for a given block. the command sequence necessary to execute a block protect is similar to that of a program. to provide added security against accidental block pro- tection, three consecutive command cycles are re- quired to initiate a block protect. in the first cycle, load command register is issued with protect setup (60h) on a0Ca7, and the bank address of the
flash 28 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory block to be protected is issued on ba0, ba1. the next command is active, which identifies a row in the block to be protected and confirms the bank address. the third cycle is write, during which block protect confirm (01h) is issued on dq0Cdq7, and the bank address is reissued. the ism status bit will be set on the following clock edge (subject to cas latencies) indicat- ing the protect operation is in progress. if the lcr/active/write is not completed on con- secutive cycles (nops and command inhibits are permitted between cycles), or the bank address changes, the write and erase status bits (sr4 and sr5) will be set and the operation will be aborted. when the ism status bit (sr7) is set to a logic 1, the protect opertation is complete. once a block protect bit has been set to a 1 (pro- tected), it can only be reset to a 0 if the unprotect all blocks command is executed. the unprotect all blocks command sequence is similar to the block pro- tect sequence; however, in the third cycle, a write is issued with unprotect all blocks confirm (d0h) and addresses are dont care. for additional infor- mation, refer to truth table 2. the blocks at locations 0 and 15 have additional security. once the block protect bits at locations 0 and 15 have been set to a 1 (protected), each bit can only be reset to a 0 if rp# is brought to v hh prior to the third cycle (write) of the unprotect operation, and held at v hh until the operation is complete (sr7 = 1). if the device protect bit is set, rp# must be brought to v hh prior to the third cycle and held at v hh until the block protect or unprotect all blocks opera- tion is complete. to check a blocks protect status, a read device con- figuration command sequence may be issued. device protect sequence executing a device protect sequence will set the device protect bit to a 1 and prevent block protect bit modification. the command sequence necessary to execute a device protect is similar to that of a pro- gram. three consecutive command cycles are re- quired to initiate a device protect. in the first cycle, load command register is issued with protect setup (60h) on a0Ca7, and a bank address is issued on ba0, ba1. the bank address is dont care, but the same bank address must be used for all three cycles. the next command is active. the third cycle is write, during which device protect (f1h) is issued on dq0Cdq7. rp# must be brought to v hh prior to regis- tration of the write command. the ism status bit will be set on the following clock edge (subject to cas laten- cies). rp# must be held at v hh until the protect op- eration is complete (sr7 = 1). once the device protect bit is set, it can only be reset to a 0 by issuing a block unprotect command with rp# at v hh during the operation. with the device protect bit set to a 1, block protect or block unprotect is prevented unless rp# is at v hh during either operation. the device protect bit does not affect program or erase operations. reset/deep power-down mode to allow for maximum power conservation, the de- vice features a very low current, deep power-down mode. to enter this mode, the rp# pin (reset/power-down) is taken to v ss 0.2v. to prevent an inadvertent reset, rp# must be held at v ss for 50ns prior to the device entering the reset mode. with rp# held at v ss , the de- vice will enter the deep power-down mode. after the device enters the deep power-down mode, a transition from low to high on rp# will result in a device power- up initialization sequence as outlined in the device initialization section. transitioning rp# from low to high after entering the reset mode but prior to enter- ing deep power-down mode (i.e., less than 100ns) will require a 1s delay prior to issuing an executable com- mand. when the device enters the deep power-down mode, all buffers excluding the rp# buffer are disabled and the current draw is a maximum of 100a at 3.6v v cc . the input to rp# must remain at v ss during deep power-down. entering the reset mode clears the sta- tus register. error handling after the ism status bit (sr7) has been set, the de- vice protect (sr3), write/protect block (sr4) and erase/ unprotect (sr5) status bits may be checked. if one or a combination of sr3, sr4, sr5 status bits has been set, an error has occurred. sr8 is set when an inadvertent power failure occurs during device initialization. the device should be reinitialized to ensure proper device operation. the ism cannot reset sr3, sr4, sr5 or sr8. to clear these bits, clear status register (50h) must be given. table 5 lists the combination of errors. program/erase cycle endurance syncflash memory is designed and fabricated to meet advanced code and data storage requirements. operation outside specification limits may reduce the number of program and erase cycles that may be performed on the device. each block is designed and processed for a minimum of 100,000-program/ erase-cycle endurance.
flash 29 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory status bit # status register bit description sr15- reserved reserved for future use. sr9 sr8 v cc power sequence status (vps) vps is set if there has been a power disruption that may 1 = power-up incomplete error result in undefined device operation. a vps error is 0 = power-up complete only cleared by re-initializing the device. sr7 ism status (isms) the isms bit displays the active status of the state machine 1 = ready when performing program or block erase. the 0 = busy controlling logic polls this bit to determine when the erase and program status bits are valid. sr6 reserved reserved for future use. sr5 erase/unprotect block status (es) es is set to 1 after the maximum number of erase cycles 1 = block erase or block is executed by the ism without a successful verify. this bit unprotect error is also set to 1 if a block unprotect operation is 0 = successful block erase or unsuccessful. es is only cleared by a clear status unprotect register command or by a reset. sr4 program/protect block status (ws) ws is set to 1 after the maximum number of program 1 = program or block protect error cycles is executed by the ism without a successful verify. 0 = successful block erase or this bit is also set to 1 if a block or device protect unprotect operation is unsuccessful. ws is only cleared by a clear status register command or by a reset. sr3 device protect status (dps) dps is set to 1 if an invalid program, erase, protect 1 = device protected, invalid operation block, protect device, or unprotect all blocks is attempted met. after one of these commands is issued, the condition 0 = device unprotected or rp# of rp#, the block protect bit, and the device protect bit is condition met compared to determine if the desired operation is allowed. must be cleared by clear status register or by a reset. sr2 bank ism status (bisms) when sr0 = 0, the bank under ism control can be sr1 banka1 ism status decoded from sr1, sr2: [0,0] bank0; [1,0] bank1; [0,1] banka0 ism status bank2; [1,1] bank3. sr1, sr2 is valid when sr7 = 0. when sr7 = 1, sr1, sr2 is reset to 0. sr0 device/bank ism status (dbs) dbs is set to 1 if the ism operation is a device-level 1 = device-level ism operation operation. a valid read to any bank can immediately 0 = bank-level ism operation follow the registration of an ism program operation. when dbs is set to 0, the ism operation is a bank-level operation. a read to the bank under ism control will output the contents of the row activated prior to the lcr/ active/write command sequence. sr1 and sr2 can be decoded to determine which bank is under ism control. sr0 is used in conjuction with sr7, and is valid when sr7 = 0. when sr7 = 1, sr0 is reset to 0. note: 1. sr3-sr5 must be cleared with clear status register prior to initiating an ism write operation for the status bits to be valid. table 3 status register bit definition 1 r vps isms r es ws dps bisms dbs 15-9 8 7 6 5 4 3 2-1 0
flash 30 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory table 4 device configuration device configuration configuration address data condition notes manufacturer compatibility id 000h 2ch manufacturer compatibility id read 1 device id 001h d3h device id read 1 block protect bit x02h dq0 = 1 block protected 2, 3 x02h dq0 = 0 block unprotected device protect bit 003h dq0 = 1 block protect modification prevented 3 003h dq0 = 0 block protect modification enabled table 5 status register error decode 4 status bits sr5 sr4 sr3 error description 5 0 0 0 no errors 0 1 0 program, block protect or device protect error 0 1 1 invalid block protect or device protect, rp# not valid (v hh ) 0 1 1 invalid block or device protect, rp# not valid 1 0 0 erase or all block unprotect error 1 0 1 invalid all block unprotect, rp# not valid (v hh ) 1 1 0 command sequencing error note: 1. dq8Cdq15 are dont care. 2. address to read block protect bit is always the third location within each block. x = 0, 4, 8, c; ba0, ba1 required. 3. dq1Cdq7 are reserved, dq8Cdq15 are dont care. 4. sr3Csr5 must be cleared using clear status register. 5. assumes that sr4 and sr5 reflect noncumulative results.
flash 31 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory complete program status-check sequence self-timed program sequence 1 note: 1. sequence may be repeated for multiple programs. 2. complete status check is not required. 3. the bank will be in array read mode. 4. status register bits 3C5 must be cleared using clear status register. load command register 40h start write column address/data status register polling sr7 = 1? complete status check (optional) program complete 3 2 active row address no yes start (program completed) sr4, 5 = 1? yes command sequence error sr4 = 1? no yes no yes no 4 program successful sr3 = 1? invalid program error 4 program error 4
flash 32 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory self-timed block erase sequence 1 complete block erase status-check sequence note: 1. sequence may be repeated to erase multiple blocks. 2. complete status check is not required. 3. the bank will be in the array read mode. 4. status register bits 3C5 must be cleared using clear status register. load command register 20h active row address start write d0h status register sr7 = 1 complete status check (optional) erase complete 3 2 yes yes no block protected? rp# = v hh no start (erase or block unprotect completed) sr4, 5 = 1? yes command sequence error sr5 = 1? no yes no yes no 4 block erase or unprotect error 4 erase or block unprotect successful sr3 = 1? invalid erase or unprotect error 4
flash 33 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory block protect sequence 1 complete block status-check sequence note: 1. sequence may be repeated for multiple block protects. 2. complete status check is not required. 3. the bank will be in array read mode. 4. status register bits 3C5 must be cleared using clear status register. yes no load command register 60h active row start write 01h status register sr7 = 1 complete status check (optional) block protect complete 3 2 yes no device protected? rp# = v hh start (block or device protect completed) sr4 = 1? block or device protect error 4 block or device protect successful sr3 = 1? invalid block/device protect error 4 sr4, 5 = 1? yes command sequence error 4 no yes no yes no
flash 34 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory device protect sequence 1 block unprotect sequence note: 1. once the device protect bit is set, it cannot be reset. 2. complete status check is not required. 3. for complete details, see complete block status check sequence. 4. the device will remain in the array read mode; a read may be issued to any bank after the write (d0h) is registered. yes no load command register 60h active row start write d0h status register complete status check (optional) all blocks unprotect complete 4 2, 3 device protected? unprotect block 0 or block 15? block 0 or block 15 protected? rp# = v hh no no no yes yes yes sr7 = 1 load command register 60h start write f1h complete status check (optional) device protect complete 2, 3 active row rp# = v hh yes no status register sr7 = 1
flash 35 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory electrical characteristics and recommended dc operating conditions (notes: 1, 2); commercial temperature (0oc t a +70oc) parameter/condition symbol min max units notes v cc supply voltage v cc 3.0 3.6 v v cc q supply voltage v cc q 3.0 3.6 v hardware protection voltage v hh 8.5 10 v (rp# only) input high voltage: v ih 2v cc q + 0.3 v logic 1; all inputs input low voltage: v il - 0.3 0.8 v logic 0; all inputs input leakage current: any input 0v v in v cc i l -5 5 a (all other pins not under test = 0v) ouput leakage current: i oz -5 5 a dqs are disabled; 0v v out v cc q output levels: output high voltage (i out = -4ma) v oh 2.4 v (i out = -100ma) v oh v output low voltage (i out = -4ma) v ol 0.4 v (i out = 100ma) v ol v absolute maximum ratings* voltage on rp# relative to v ss .................... -1v to +10v voltage on v cc , v cc p or v cc q supply or inputs, relative to v ss ....................................... -1v to +3.6v voltage on i/o pins relative to v ss .............. v cc q 0.3v operating temperature, t a (ambient) ........................................ 0oc to +70oc storage temperature (plastic) ........... -55oc to +150oc power dissipation ........................................................ 1w short circuit output current ................................ 50ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up. (v cc , v cc p and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.)
flash 36 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory capacitance parameter symbol min max units notes input capacitance: clk c i 1 2.5 6.5 p f 7 input capacitance: all other input-only pins c i 2 2.5 6.5 p f 7 input/output capacitance: dqs c io 4.0 7.0 p f 7 note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up. (v cc , v cc p, and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.) 3. i cc specifications are tested after the device is properly initialized. 4. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 5. the i cc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 6. address transitions average one transition every 30ns. 7. this parameter is sampled. v cc = v cc q; f = 1 mhz, t a = +25oc. i cc specifications and conditions (notes: 1, 2, 3); commercial temperature (0oc t a +70oc) max parameter/condition symbol -10 -12 units notes v cc operating current: i ccr 1 125 120 ma 4,5,6 active mode; burst = 2; read; t ck = 15ns; t rc = t rc (min); cas latency = 3 v cc operating current: i ccr 2 100 95 ma 4, 5, 6 burst mode; continuous burst; all banks active; read; t ck = 15ns; cas latency = 3 v cc standby current: i ccs 1 10 10 ma active mode; cke = low; burst in progress v cc standby current: i ccs 2 22ma power-down mode; cke = low; no burst in progress v cc deep power-down current: i ccdp 300 300 a rp# = v ss 0.2v program current i ccw + i ppw 60 60 ma v cc p operating current: i ppr 1 250 125 a active mode; burst = 2; read; t rc = t rc (min); cas latency = 3 v cc p operating current: i cc e +i pp e 80 80 ma erase current v cc p deep power-down current: i ppdp 11a rp# = v ss 0.2v
flash 37 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory electrical characteristics and recommended ac operating conditions (notes: 1, 2, 3, 4, 5); commercial temperature (0oc t a +70oc) ac characteristics -10 -12 parameter sym min max min max units notes access time from clk (pos. edge) cl = 3 t ac 7 9 ns cl = 2 t ac 9 10 ns cl = 1 t ac 27 27 ns address hold time t ah 2 2 ns address setup time t as 3 3 ns clk high level width t ch 3.5 4 ns clk low level width t cl 3.5 4 ns clock cycle time cl = 3 t ck 10 12 ns cl = 2 t ck 15 15 ns cl = 1 t ck 30 30 ns cke hold time t ckh 2 2 ns cke setup time t cks 3 3 ns cs#, ras#, cas#, we#, dqm hold time t cmh 2 2 ns cs#, ras#, cas#, we#, dqm setup time t cms 3 3 ns data-in hold time t dh 2 2 ns data-in setup time t ds 3 3 ns data-out high-impedance time cl = 3 t hz 8 9 ns 6 cl = 2 t hz 10 10 ns 6 cl = 1 t hz 15 15 ns 6 data-out low-impedance time t lz 2 2 ns data-out hold time t oh 3 3 ns active command period t rc 90 100 ns active to read or write delay t rcd 30 30 ns active bank a to active bank b command t rrd 20 20 ns transition time t t 0.3 1.2 1 1.2 ns 7 note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100s is required after power-up. (v cc , v cc p, and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.) 3. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. outputs measured at 1.5v with equivalent load: q 50pf 5. ac timing and i cc tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 6. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 7. ac characteristics assume t t = 1ns.
flash 38 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory ac functional characteristics (notes: 1-6); commercial temperature (0oc t a +70oc) parameter symbol -10 -12 units notes read/write command to read/load command register command t ccd 1 1 t ck 7 cke to clock disable or power-down entry mode t cked 1 1 t ck 8 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 8 dqm to input data delay t dqd 0 0 t ck 7 dqm to data mask during writes t dqm 0 0 t ck 7 dqm to data high-impedance during reads t dqz 2 2 t ck 7 write command to input data delay t dwd 0 0 t ck 7 data-in to active command t dal 4 4 t ck data-in to active terminate command t dpl 1 1 t ck load mode register command to active command t mrd 2 2 t ck 7 data-out to high-z from active terminate command cl = 3 t roh 3 3 t ck 7 cl = 2 t roh 2 2 t ck 7 cl = 1 t roh 1 1 t ck 7 note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100s is required after power-up. (v cc , v cc p, and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.) 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 1.5v with equivalent load: q 50pf 6. ac timing and i cc tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 7. required clocks specified by jedec functionality and not dependent on any timing parameter. 8. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. erase and program timing characteristics commercial temperature (0oc t a +70oc) -10/-12 parameter min max units word program time 5 5,000 s block erase time 1.1 13 s
39 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory initialize and load mode register *cas latency indicated in parentheses. timing parameters -10 -12 symbol* min max min max units t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns -10 -12 symbol* min max min max units t ck (1) 30 30 ns t ckh 2 2 ns t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t mrd 2 2 t ck note: 1. rp# = v hh or v ih 2. v cc , v cc p, v cc q = 3.3v 3. the nvmode register contents are automatically loaded into the mode register upon power-up initialization, load mode register cycle is required to enter new mode register values. 4. jedec and pc100 specify three clocks. 5. if cs is high at clock time, all commands applied are nop, with cke a dont care. t ch t cl cke t0 clk t1 tn + 3 tn + 4 command dq address opcode t mrd program mode register 3, 4, 5 t cms power-up: 2 v cc , v cc p, v cc q, clk stable t = 100s t ah t as row load mode register nop active high-z dqm v cc , v cc p, v cc q dont care undefined tn+1 tn + 2 t ck t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) rp# 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
40 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t dh 2 2 ns t ds 3 3 ns t hz (3) 8 9 ns t hz (2) 10 10 ns t hz (1) 15 15 ns t lz 2 2 ns t oh 3 3 ns clock suspend mode 1 *cas latency indicated in parentheses. timing parameters -10 -12 symbol* min max min max units t ac (3) 7 9 ns t ac (2) 9 10 ns t ac (1) 27 27 ns t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns t ck (1) 30 30 ns t ckh 2 2 ns -10 -12 symbol* min max min max units note: 1. for this example, the burst length = 2, cas latency = 3. 2. x16: a0Ca7. t ch t cl t ck t ac t lz dqm clk a0Ca11 dq ba t oh d out m t ah t as t ah t as t ac t hz d out m+1 command t cmh t cms t cmh t cms nop nop nop nop nop read dont care undefined cke t cks t ckh bank column m 2 t ckh t cks t0 t1 t2 t3 t4 t5
41 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory read 1 t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t hz (3) 8 9 ns t hz (2) 10 10 ns t hz (1) 15 15 ns t lz 2 2 ns t oh 3 3 ns t rc 90 100 ns t r c d 30 30 n s *cas latency indicated in parentheses. timing parameters -10 -12 symbol* min max min max units t ac (3) 7 9 ns t ac (2) 9 10 ns t ac (1) 27 27 ns t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns t ck (1) 30 30 ns t ckh 2 2 ns -10 -12 symbol* min max min max units note: 1. for this example, the burst length = 4, cas latency = 2. 2. x16: a0Ca7. 3. t ras and t rp are referenced to show compatibility with sdram timings; no values are given. t ch t cl t ck t ac t lz t rp 3 t ras 3 t rcd cas latency t rc dqm cke clk a0Ca11 dq ba t oh d out m t ah t as t ah t as column m 2 row bank bank row bank dont care undefined t hz t oh d out m+3 t ac t oh t ac t oh t ac d out m+2 d out m+1 command t cmh t cms t cmh t cms nop nop nop active nop read nop active nop t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8
42 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory alternating bank read accesses 1 t ckh 2 2 ns t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t lz 2 2 ns t oh 3 3 ns t rc 90 100 ns t r c d 30 30 n s t r r d 20 20 n s *cas latency indicated in parentheses. timing parameters -10 -12 symbol* min max min max units t ac (3) 7 9 ns t ac (2) 9 10 ns t ac (1) 27 27 ns t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns t ck (1) 30 30 ns -10 -12 symbol* min max min max units note: 1. for this example, cas latency = 2. 2. x16: a0Ca7. t ch t cl t ck t ac t lz dqm clk a0Ca11 dq ba t oh d out m t ah t as t ah t as column m 2 row row dont care undefined t oh d out m+3 t ac t oh t ac t oh t ac d out m+2 d out m+1 command t cmh t cms t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read column b 2 active row bank 0 bank 0 bank 1 bank 1 bank 0 cke t ckh t cks t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 1 cas latency - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8
43 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory read C full-page burst 1 t ckh 2 2 ns t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t hz (3) 8 9 ns t hz (2) 10 10 ns t hz (1) 15 15 ns t lz 2 2 ns t oh 3 3 ns t r c d 30 30 n s *cas latency indicated in parentheses. timing parameters -10 -12 symbol* min max min max units t ac (3) 7 9 ns t ac (2) 9 10 ns t ac (1) 27 27 ns t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns t ck (1) 30 30 ns -10 -12 symbol* min max min max units note: 1. for this example, the cas latency = 2. 2. x16: a0Ca7. t ch t cl t ck t ac t lz t rcd cas latency dqm cke clk a0Ca11 dq ba oh d out m t ah t as t ac t oh d out m+1 row t hz t ac t oh d out m+1 t ac t oh d out m+2 t ac t oh d out m-1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed. 256 (x16) locations within the same row. dont care undefined command t cmh t cms t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop column m 2 t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 t3 t4 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 3
44 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory read C dqm operation 1 t ckh 2 2 ns t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t hz (3) 8 9 ns t hz (2) 10 10 ns t hz (1) 15 15 ns t lz 2 2 ns t oh 3 3 ns t r c d 30 30 n s *cas latency indicated in parentheses. timing parameters -10 -12 symbol* min max min max units t ac (3) 7 9 ns t ac (2) 9 10 ns t ac (1) 27 27 ns t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns t ck (1) 30 30 ns -10 -12 symbol* min max min max units note: 1. for this example, the burst length = 4, cas latency = 2. 2. x16: a0Ca7. t ch t cl t ck t rcd cas latency dqm cke clk a0Ca11 dq ba bank row bank dont care undefined t ac lz d out m t oh d out m+3 d out m+2 t t hz lz t command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t ah t as t cms t cmh t cms t cmh column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8
45 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory note: 1. for this example, read burst length = 2, cas = 3. 2. com-code = 40h for write, 20h for erase (see truth table 2). 3. column address is dont care for erase operation. 4. d in = d0h (erase confirm) for erase operation. program/erase 1 (bank a followed by read to bank b ) t ckh 2 2 ns t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t dh 2 1.5 ns t ds 3 3 ns timing parameters -10 -12 symbol* min max min max units t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns t ck (1) 30 30 ns -10 -12 symbol* min max min max units *cas latency indicated in parentheses. t ch t cl t ck dqm cke clk a0 C a11 ba dq t cmh t cms bank b row bank a d in 4 m t dh t ds t ds command t cmh t cms read nop active nop write lcr nop bank a column n bank a t ah t as t dh t ckh t cks nop nop nop column 3 m t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 comcode 2 dont care undefined t rcd d out nd out n + 1 high-z
46 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory program/erase 1 (bank a followed by read to bank a ) t ch t cl t ck dqm cke clk a0Ca11 ba dq t ah t as bank a row bank a dont care undefined d in 5 m t dh t ds command t cmh t cms active nop write lcr bank a t ah t as t ckh t cks column 4 m t0 t1 t2 t3 comcode 2 ism program or erase operation is complete t = 1 0s typical/word t cmh t cms read nop column n nop t4 t5 t6 t ds t row column bank a bank a high-z sr7 = 1 sr7 = 0 tn tn + 1 tn + 2 tn + 3 bank a dh d out n d out nop active nop read nop nop nop tn + 4 tn + 5 nop read 3 note: 1. active/read or read will output the contents of the row activated prior to the lcr/active/write command sequence. this exampl e illustrates the timing for activating a new row in bank a . for this example, read burst length = 2, cas latency = 2. 2. com-code = 40h for program, 20h for erase (see truth table 2). 3. lcr/active cycles must be initiated prior to read according to truth table 2 for a status register read command sequence. 4. column address is dont care for erase operation. 5. d in = d0h (erase confirm) for erase operation. t ckh 2 2 ns t cks 3 3 ns t cmh 2 2 ns t cms 3 3 ns t dh 2 2 ns t ds 3 3 ns timing parameters -10 -12 symbol* min max min max units t ah 2 2 ns t as 3 3 ns t ch 3.5 4 ns t cl 3.5 4 ns t ck (3) 10 12 ns t ck (2) 15 15 ns t ck (1) 30 30 ns -10 -12 symbol* min max min max units *cas latency indicated in parentheses.
47 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory 54-pin tsop type ii (400 mil) see detail a .20 .05 1.00 (2x) .75 (2x) .80 typ .71 10.24 10.08 .18 .13 .60 .40 pin #1 id detail a 22.30 22.14 .45 .30 1.2 max .10 .25 11.86 11.66 .80 typ .10 (2x) 2.80 note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron and syncflash are registered trademarks and the micron logo, and m logo are trademarks of micron technology, inc. data sheet designation this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
48 4 meg x 16 syncflash micron technology, inc., reserves the right to change products or specifications without notice. MT28S4M16LC_6.p65 C rev. 6, pub. 9/01 ?2001, micron technology, inc. 4 meg x 16 syncflash memory revision history rev. 6 ......................................................................................................................... ................................................ 9/01 ? added erase and program timing characteristics ? updated the device protect sequence ? removed the preliminary designation rev. 5, preliminary ............................................................................................................ .................................. 7/01 changed t ah, t ckh, t cmh, t dh from 1ns to 2ns rev. 4, advance ................................................................................................................ .................................... 5/01 changed deep power-down current from 100a to 300a rev. 3, advance ................................................................................................................ .................................... 4/01 changes to v cc p operating current changes to max capacitance parameters rev. 2, advance ................................................................................................................ .................................... 2/01 changes to absolute maximum ratings changes to i cc specifications and conditions original document, rev. 11/00, advance ......................................................................................... ................ 11/00

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